1. Field of the Invention
The present invention relates generally to dielectric layers, as employed within microelectronic fabrications. More particularly, the present invention relates to methods for inhibiting microelectronic damascene processing induced physical degradation of dielectric layers, and in particular low dielectric constant dielectric layers, as employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications, in comparison with conventional dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications, such as but not limited to conventional silicon oxide dielectric materials, conventional silicon nitride materials and conventional silicon oxynitride materials as employed for forming microelectronic dielectric layers within microelectronic fabrication, where such conventional dielectric materials typically have a dielectric constant. Such comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications may include, but are not limited to, spin-on-polymer (SOP) dielectric materials, spin-on-glass (SOG) dielectric materials, amorphous carbon dielectric materials, fluorosilicate glass (FSG) dielectric materials and aerogel (i.e., air entrained) dielectric materials.
Comparatively low dielectric constant dielectric materials are desirable within the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as within such applications comparatively low dielectric constant dielectric materials provide microelectronic fabrications with enhanced microelectronic fabrication speed, reduced microelectronic fabrication patterned conductor layer parasitic capacitance and reduced microelectronic fabrication patterned conductor layer cross-talk.
While comparatively low dielectric constant dielectric materials are thus desirable in the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications, comparatively low dielectric constant dielectric constant dielectric materials are nonetheless not entirely without problems within microelectronic fabrications when employed for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications. In that regard, and insofar as comparatively low dielectric constant dielectric materials typically have compromised physical properties in comparison with conventional dielectric materials, microelectronic dielectric layers when employed within microelectronic fabrications and formed of comparatively low dielectric constant dielectric materials often suffer from microelectronic processing induced physical degradation, such as but not limited to cracking and delamination, when fabricating a microelectronic fabrication while employing a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
It is thus desirable in the art of microelectronic fabrication to provide methods through which microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials may be fabricated within microelectronic fabrications with inhibited microelectronic fabrication processing induced physical degradation.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic dielectric layers, and in particular microelectronic dielectric layers formed of low dielectric constant dielectric materials, with desirable properties in the art of microelectronic fabrication.
For example, Chen et al., in U.S. Pat. No. 5,973,387, discloses a method for reducing within a gap filling microelectronic dielectric layer formed interposed between a series of patterns which comprises a densely patterned microelectronic conductor layer formed over a microelectronic substrate employed within a microelectronic fabrication a cracking at a juncture of: (1) the series of patterns which comprises the densely patterned microelectronic conductor layer; and (2) an open area of the microelectronic substrate. To realize the foregoing object, the method employs within a pattern which comprises the densely patterned microelectronic conductor layer, where the pattern in turn adjoins the open area of the microelectronic substrate, a sidewall tapered in the direction of the open area of the microelectronic substrate.
In addition, Zhao, in U.S. Pat. No. 6,071,809, discloses a method for fabricating within a microelectronic fabrication a dual damascene structure formed employing a microelectronic dielectric layer formed of a low dielectric constant dielectric material, wherein there is avoided within the dual damascene structure delamination of the microelectronic dielectric layer when forming within the dual damascene structure a chemical mechanical polish (CMP) planarized patterned microelectronic conductor layer which also comprises the dual damascene structure. To realize the foregoing object, the method employs formed upon the microelectronic dielectric layer when forming the dual damascene structure a composite hard mask layer comprising a silicon nitride hard mask material having formed thereupon a silicon oxide hard mask material, wherein the silicon oxide hard mask material serves as a sacrificial mask material when chemical mechanical polish (CMP) planarizing within the dual damascene structure the chemical mechanical polish (CMP) planarized patterned microelectronic conductor layer within the dual damascene structure.
Further, Shields, in U.S. Pat. No. 6,084,290, discloses a microelectronic fabrication and a method for fabricating the microelectronic fabrication, wherein there is formed within the microelectronic fabrication an interlayer microelectronic dielectric layer formed of a hydrogen silsesquioxane (HSQ) low dielectric constant dielectric material absent cracking within the interlayer microelectronic dielectric layer formed of the hydrogen silsesquioxane (HSQ) low dielectric constant dielectric material. To realize the foregoing object, the interlayer microelectronic dielectric layer formed of the hydrogen silsesquioxane (HSQ) low dielectric constant dielectric material is formed within the microelectronic fabrication upon a planar substrate layer, rather than a topographic substrate layer.
Finally, Sabota et al., in U.S. Pat. No. 6,133,619, discloses a microelectronic fabrication and a method for fabricating the microelectronic fabrication, wherein the microelectronic fabrication comprises a microelectronic dielectric layer formed of a low dielectric constant hydrogen silsesquioxane (HSQ) dielectric material formed interposed between a series of patterns which comprises a patterned microelectronic conductor layer within the microelectronic fabrication, and wherein there is reduced a hydrogen silsesquioxane (HSQ) dielectric material outgassing induced delamination of an upper lying barrier dielectric layer formed upon an upper lying patterned conductor layer within the microelectronic fabrication. To realize the foregoing object, there is formed upon the microelectronic dielectric layer formed of the low dielectric constant hydrogen silsesquioxane (HSQ) dielectric material a silicon oxide cap dielectric layer of thickness at least about 1000 angstroms.
Desirable in the art of microelectronic fabrication are additional methods through which microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials may be formed within microelectronic fabrications with inhibited microelectronic fabrication processing induced physical degradation.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming a low dielectric constant dielectric layer for use within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the low dielectric constant dielectric layer is formed with inhibited microelectronic processing induced physical degradation.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein a method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention three chemical mechanical polish (CMP) planarizing methods for forming a series of damascene structures within a series of microelectronic fabrications.
Within a first of the three chemical mechanical polish (CMP) planarizing methods, there is first provided a substrate. There is then formed over the substrate a patterned dielectric layer defining an aperture, where a sidewall of the patterned dielectric layer adjacent an edge of the substrate is laterally offset from the edge of the substrate by a lateral offset width. There is then formed over the patterned dielectric layer a blanket conductor layer which covers the sidewall of the patterned dielectric layer adjacent the edge of the substrate. Finally, there is then chemical mechanical polish (CMP) planarized the blanket conductor layer to form a chemical mechanical polish (CMP) planarized patterned conductor layer within the aperture and a chemical mechanical polish (CMP) planarized patterned conductor residue layer interposed between the sidewall of the patterned dielectric layer and the edge of the substrate.
Within a second of the three chemical mechanical polish (CMP) planarizing methods, there is also first provided a substrate. There is then also formed over the substrate a patterned dielectric layer defining an aperture, where a sidewall of the patterned dielectric layer adjacent an edge of the substrate is laterally offset from the edge of the substrate by a first lateral recess width. There is then formed over the patterned dielectric layer a patterned conductor layer which fills the aperture, where a sidewall of the patterned conductor layer is further laterally offset from the sidewall of the patterned dielectric layer by a second lateral offset width. There is then formed over the patterned conductor layer a blanket second dielectric layer which covers the sidewall of the patterned conductor layer and the sidewall of the patterned dielectric layer. Finally, there is then chemical mechanical polish (CMP) planarized the blanket second dielectric layer and the patterned conductor layer to form a chemical mechanical polish (CMP) planarized patterned conductor layer within the aperture and a chemical mechanical polish (CMP) planarized patterned second dielectric layer interposed between the sidewall of the patterned first dielectric layer and the edge of the substrate.
Within a third of the three chemical mechanical polish (CMP) planarizing methods, there is also first provided a substrate. There is then also formed over the substrate a first dielectric layer. There is then formed over the first dielectric layer a patterned second dielectric layer defining an aperture, where a sidewall of the patterned second dielectric layer is laterally offset from a sidewall of the first dielectric layer by a second lateral offset width. There is then formed over the first dielectric layer and the patterned second dielectric layer and completely filling the aperture a blanket conductor layer. Finally, there is then chemical mechanical polish (CMP) planarized the blanket conductor layer to form a chemical mechanical polish (CMP) planarized patterned conductor layer within the aperture.
The present invention provides a series of methods for forming a low dielectric constant dielectric layer for use within a microelectronic fabrication, wherein the low dielectric constant dielectric layer is formed with inhibited microelectronic processing induced physical degradation.
The present invention realizes the foregoing objects by providing a series of chemical mechanical polish (CMP) planarizing methods for forming a series of damascene structures within a series of microelectronic fabrications, wherein by employing a series of lateral offset widths with respect to: (1) a patterned dielectric layer sidewall and a substrate edge; (2) a patterned conductor layer and a patterned dielectric layer; and (3) a patterned second dielectric layer and a patterned first dielectric layer, within the series of microelectronic fabrications, and where the patterned dielectric layers may be formed of a low dielectric constant dielectric material, a series of chemical mechanical polish (CMP) planarized patterned conductor layers formed employing the series of chemical mechanical polish (CMP) planarizing methods is formed with inhibited microelectronic damascene processing induced physical degradation to the series of patterned dielectric layers.
The methods of the present invention are readily commercially implemented. As will be illustrated in greater detail within the context of the Description of the Preferred Embodiments, as set forth below, the methods of the present invention may be practiced employing materials as are otherwise generally conventional in the art of microelectronic fabrication, but employed within the context of specific process limitations to provide the methods of the present invention. Since it is thus a series of process limitations which provides at least in part the present invention, rather than the existence of materials which provides the present invention, the methods of the present invention are readily commercially implemented.